Annealing processors are designed specifically for addressing combinatorial optimisation problems, where the task is to find the best solution from a finite set of possibilities.

With CMOS ICs it is necessary for the components of annealing processors to be fully “coupled.” However, the complexity of this coupling directly affects the scalability of the processors.

Led by Professor Takayuki Kawahara, researchers from the Tokyo University of Science, have developed and successfully tested a scalable, fully coupled annealing processor incorporating 4096 spins on a single board with 36 CMOS chips.